на ISA карточке развести IRQ (isa hardware scheme io)
Ключевые слова: isa, hardware, scheme, io, (найти похожие документы)
_ RU.UNIX (2:5077/15.22) _____________________________________________ RU.UNIX _
From : Valentin Davydov 2:5020/400 Tue 08 Feb 28 09:20
Subj : на ISA карточке развести IRQ
________________________________________________________________________________
From: Valentin Davydov <val@sqdp.trc-net.co.jp>
> From: "Igor Demchenko" <dia@aero.kamchatka.ru>
> Date: 8 Feb 2000 07:39:40 +0300
>
>> Кто тебе мешает на самой карточке развести прерывания на 2 и, скажем, 5?
>
>Карточка и мешает. Там можно только I/O разнести, а о прерываниях не слова.
>Может быть их где-нибудь можно перепаять? Вопрос, только как? Как найти
>нужное.
Берёшь паяльник, резак и распечатку, и делаешь.
ISABUS Pinout:
(just ignore the 16-bit extension if you want the 8-bit bus)
:-) --Tim
AT I/0 CHANNEL (SYSTEM BUS) PINOUTS
Pin Signal Description Direction*
-------------------------------------------------------------------------------
A1 -I/0 CH CK I/0 channel check;active low=parity error In
A2 SD7 Data bit 7 In/Out
A3 SD6 Data bit 6 In/Out
A4 SD5 Data bit 5 In/Out
A5 SD4 Data bit 4 In/Out
A6 SD3 Data bit 3 In/Out
A7 SD2 Data bit 2 In/Out
A8 SD1 Data bit 1 In/Out
A9 SDO Data bit 0 In/Out
A10 -I/0 CH RDY I/0 Channel ready; pulled low to lengthen memory cycles In
Al1 AEN Address enable; active high when DMA controls bus out
A12 SA19 Address bft 19 out
A13 SA18 Address bit 18 out
A14 SA17 Address bit 17 Out
A15 SA16 Address bit 16 out
A16 SA15 Address bit 15 out
A17 SA14 Address bit 14 out
A18 SA13 Address bit 13 Out
A19 SA12 Address bit 12 Out
A20 SA11 Address bit 11 Out
A21 SA1O Address bit 10 out
A22 SA9 Address bit 9 Out
A23 SAS Address bit 8 Out
A24 SA7 Address bit 7 Out
A25 SA6 Address bit 6 out
A26 SAS Address bit 5 Out
A27 SA4 Address bit 4 Out
A28 SA3 Address bit 3 Out
A29 SA2 Address bit 2 Out
A30 SA1 Address bit 1 out
A31 SA0 Address bit 0 Out
B1 GROUND
B2 RESET DRV Active high lo reset or Initialize system logic out
B3 +5Vdc
B4 IRQ9 Interrupt request 9 In
B5 -5Vdc
B6 DRQ2 DMA request 2 In
B7 -12Vdc
B8 -CARD SLCTD Card selected; activated by cards In XT's slot J8 In
B9 +12Vdc
B10 GROUND
B11 -MEMW Memory write Out
B12 -MEMR Memory read Out
B13 -IOW I/O write In/Out
B14 -IOR I/O read In/Out
B15 -DACK3 DMA acknowledge 3 Out
B16 DRQ3 DMA request 3 In
B17 -DACK1 DMA acknowledge 1 Out
B18 DRQ1 DMA request 1 In
B19 -REFRESH Refresh In/Out
B20 CLOCK System clock (67 ns,6 or 8MHz);50% duty cycle Out
B21 IRQ7 Interrupt request 7 In
B22 IRQ6 Interrupt request 6 In
B23 IRQ5 Interrupt request 5 In
B24 IRQ4 Intertupt request 4 In
B25 IRQ3 Interrupt request 3 In
B26 -DACK2 DMA acknowledge 2 Out
B27 T/C Terminal count: pulses high when DMA term count reached Out
B28 ALE Address latch enable Out
B29 +5Vdc
B30 OSC High-speed clock (70 ns, 14.31818Mhz),50%duty cycle Out
B31 GROUND
16-bit AT extension
-------------------
C1 SBHE System bus high enable (data available on SD8-15) In/Out
C2 LA23 Address bit 23 (unlatched) In/Out
C3 LA22 Address bit 22 (unlatched) In/out
C4 LA21 Address bit 21 (unlatched) In/Out
C5 LA20 Address bit 20 (unlatched) In/Out
C6 LA19 Address bit 19 (unlatched) In/Out
C7 LA18 Address bit 18 (unlatched) In/Out
C8 LA17 Address bit 17 (unlatched) In/Out
C9 -MEMR Memory read (active on all memory read cycles) In/Out
C10 -MEMW Memory write (active on all memory write cycles) In/Out
C11 SD08 Data bit 8 In/Out
C12 SD09 Data bit 9 In/Out
C13 SD10 Data bit 10 In/Out
C14 SD11 Data bit 11 In/Out
C15 SD12 Data bit 12 In/Out
C16 SD13 Data bit 13 In/Out
C17 SD14 Data bit 14 In/Out
C18 SD15 Data bit 15 In/Out
D1 -MEM CS16 Memory 16-bit chip select (1 wait, 16-bit memory cycle) In
D2 -I/O CSI6 I/O 16-bit chip select (1 wait, 16-bit I/O cycle) In
D3 IRQ10 Interrupt request 10 In
D4 IRQ11 Interrupt request 11 In
D5 IRQ12 Interrupt request 12 In
D6 IRQ15 Interrupt request 13 In
D7 IRQ14 Interrupt request 14 In
D8 -DACK0 DMA acknowledge 0 Out
D9 DRQO DMA request 0 In
D10 -DACK5 DMA acknowledge 5 Out
D11 DRQ5 DMA request 5 In
D12 -DACK6 DMA acknowledge 6 Out
D13 DRQ6 DMA request 6 In
D14 -DACK7 DMA scknowledge 7 Out
D15 DRQ7 DMA request 7 In
D16 +5Vdc
D17 -MASTER Used with DRQ to gain control of system In
D18 Ground
*-From system board
Note:- All signals are at standard TTL levels.
- Connector is a 62-pin edge connector with a
secondary 36-pin edge connector.
- A or C=component side of board;
numbers start closest to rear panel of machine.
Source:IBM PC/AT Technical Reference, pages 1-25 through 1-37
--- ifmail v.2.15dev4
* Origin: Demos online service (2:5020/400)
Vova
